********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Aug 11, 2014
*ECN S14-1600, Rev. C
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SI1302DL 4 1 2
M1  3 1 2 2 NMOS W=40394u L=0.50u 
M2  2 1 2 4 PMOS W=40394u L=0.70u
R1  4 3     RTEMP 250E-3
CGS 1 2     28E-12
DBD 2 4     DBD
**************************************************************************
.MODEL  NMOS         NMOS (LEVEL  = 3               TOX    = 5E-8
+ RS     = 105E-3          RD     = 0               NSUB   = 1.57E17   
+ kp     = 2.77E-5         UO     = 650             
+ VMAX   = 0               XJ     = 5E-7            KAPPA  = 10E-2
+ ETA    = 1E-4            TPG    = 1  
+ IS     = 0               LD     = 0                             
+ CGSO   = 0               CGDO   = 0               CGBO   = 0 
+ TLEV   = 1               BEX    = -1.5            TCV    = 4.1E-3
+ NFS    = 0.8E12          DELTA  = 0.1)
*************************************************************************
.MODEL  PMOS         PMOS (LEVEL  = 3               TOX    = 5E-8
+NSUB    = 3E16            TPG    = -1)   
*************************************************************************
.MODEL DBD D (CJO=27E-12 VJ=.38    M=0.28
+FC=0.1 IS=1E-12 TT=6.3E-8 N=1 BV=30.5)
*************************************************************************
.MODEL RTEMP R (TC1=5.5E-3   TC2=5.5E-6)
*************************************************************************
.ENDS
 
